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| (R) L4922 VERY LOW DROP REGULATOR WITH RESET .VERYLOWDROP( .LOWQUI .PRECI .POWERON.REVERSEBATTERYPROTECTI .SHORTCI .THERMALSHUTDOWN DESCRIPTION max. 0.9 V at 1 A) OVER FULL OPERATING TEMPERATURE RANGE (- 40 / + 125C) ESCENT CURRENT (max 70 mA at 1 A) OVER FULL T RANGE SE OUTPUT VOLTAGE (5 V 4 %) OVER FULL T RANGE OFF INFORMATION WITH SETTABLE DELAY ON RCUIT PROTECTION Pen tawatt O RDERING NUMBER : L4922 The L4922is a high currentmonolithic voltage regulator with very low voltage drop (0.70 V max at 1 A, TJ = 25 C). The device is internally protected against load dumps transient of + 60V, reverse polarity, over- heatingand outputshort circuit : thanks toted for the automotive and industrial applications. BLOCK DIAGRAM June 2000 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/6 L4922 ABSOLUTE MAXIMUM RATINGS Symbol Vi Vr VD TJ Top Tstg DC Input Voltage DC Reverse Voltage Positive Load Dump Protection (t = 300ms) Junction Temperature Range Operating Temperature Range Storage Temperature Range Parameter Value 35 -18 60 -40 to 150 -40 to 125 -55 to 150 Unit V V V C C C N ote: T he circuit is ESD protected according to MIL-STD -883C THERMAL DATA Symbol Rth j-case Parameter Thermal Resistance Junction-case Max. Value 3.5 Unit C/W PIN CONNECTION (Top view) FUNCTIONAL DESCRIPTION The operating principle of the voltage regulator is basedon thereference,the error amplifier,the driver and the power PNP. This stage uses an Isolated CollectorVertical PNP transistor which allowsto obtain very low dropout voltage (typ. 450mV) and low quiescent current (IQ = 20mA typically at Io = 1A). Thanks to these features the device is particularly suited when the power dissipation must be limited as, for example, in automotive or industrial applications supplied by battery. The three gain stages (operational amplifier, driver and power PNP) require the external capacitor (Comin = 22F) to guarantee the global stability of the system. The antisaturationcircuit allowsto reduce drastically the current peak which takes place during the start up. The reset function is LOW active when the output voltage level is lower than the reset threshold voltage VRthOFF (typ.value : Vo - 150mV).When the output voltage is higher thanVRthON the reset becomes HIGH aftera delaytime settablewith the externalcapacitorCd. Typicallytd =20ms, Cd = 0.1F. The reset and delay threshold hysteresis improve the noise immunity allowing to avoid false switchings. The typical reset output waveform is shown in fig. 1. 2/6 L4922 ELECTRICAL CHARACTERISTICS (Vi = 14. 4V, - 40C TJ + 125C unless otherwise specified) Symbol Vi Vo VLine SVR Parameter Operating Input Voltage Output Voltage Line Regulation Supply Voltage Rejection Test Conditions (*) Note 1 Io = 0mA to 1A TJ = 25C Vi = 6 to 26V; IO = 10mA Io = 700mA f = 120Hz; Co = 47F Vi = 12Vdc + 5Vpp Io = 10mA to 1A TJ = 25C, IO = 1A Over Full T, Io = 1A Iq ISC VR VRT peak IR tD VRthOFF Quiescent Current Short Circuit Current Rset Output Saturation Voltage Power On-Off Reset out Peak Voltage Reset Output Leakage Current (high level) Reset Pulse Delay Time Power OFF Vo Threshold 1.5V < VO < VRT (off), IR = 1.6mA 3V < VO < V RT (off), IR = 8mA 1K Reset Pull-up to VO Vo in Regul. VR = 5V CD = 100nF Vo @ Reset out H to L Transition; TJ = 25C - 40C TJ + 125C V4 = 3V Vo @ Reset out L to H Transition Reset out = "1" H to L Transition Reset out = "0" L to H Transition V6H Delay Comparator Hysteresis 3.2 3.7 4 500 4.75 4.70 20 Vo -0.15 20 Vo - VrthOFF + 0.03V 0.04V 3.8 4.4 0.65 Io = 10mA Io = 1A 7 25 1.8 0.40 0.40 1.0 50 Min. 6 4.8 4.9 5 55 Typ. Max. 26 5.2 5.1 25 Unit V V V mV dB VLOAD Vi - Vo Load Regulation Dropout Voltage 15 0.45 50 0.70 0.90 12 70 mV V V mA mA A V V V A ms V V A V V V mV IC6 VRthON V4 Delay Capacitor Charging Current (current generator) Power ON Vo Threshold Delay Comparator Threshold (*) Note 1 : The device is not operating within the range : 26 V < Vi < 37 V. EXTERNAL COMPENSATION Since the purposeof a voltageregulatoris to supply a fixed output voltage in spite of supply and load variations, the open loop gain of the regulator must be very high at low frequencies.This may cause instability as a result of the various poles present in the loop. To avoid this instability dominant pole compensationis used to reduce phase shiftsdue to other poles at the unity gain frequency. The lower the frequencyof theseother poles, the greater must be the capacitor used to create the dominant pole for the same DC gain. Where the output transistor is a lateral PNP type there is a pole in the regulation loop at a frequency too low to be compensated by a capacitor wich can be integrated. An external compensation is therefore necessary so a very high value capacitor must be connected from the output to ground. Theparassitic equivalentseries resistanceof thecapacitor used adds a zero to the regulation loop. This zero may compromise the stability of the system since its effect tends to cancel the effect of the pole added. In regulatorsthis ESR must be less than 3 and the minimum capacitor value is 47F. 3/6 L4922 Figure 1 : Typical Reset Output Waveform. Figure 2 : Typical Application Circuit. (*) RECOMMENDED VALUE : C 0 = 47 F, ESR < 10 ohm, (Iout > 10 mA) OVER FULL T range. 4/6 L4922 mm TYP. inch TYP. DIM. A C D D1 E E1 F F1 G G1 H2 H3 L L1 L2 L3 L4 L5 L6 L7 L9 M M1 V4 MIN. 2.4 1.2 0.35 0.76 0.8 1 3.2 6.6 10.05 17.55 15.55 21.2 22.3 2.6 15.1 6 4.23 3.75 3.4 6.8 17.85 15.75 21.4 22.5 MAX. 4.8 1.37 2.8 1.35 0.55 1.19 1.05 1.4 3.6 7 10.4 10.4 18.15 15.95 21.6 22.7 1.29 3 15.8 6.6 MIN. 0.094 0.047 0.014 0.030 0.031 0.039 0.126 0.260 0.396 0.691 0.612 0.831 0.878 0.102 0.594 0.236 0.134 0.268 0.703 0.620 0.843 0.886 MAX. 0.189 0.054 0.110 0.053 0.022 0.047 0.041 0.055 0.142 0.276 0.409 0.409 0.715 0.628 0.850 0.894 0.051 0.118 0.622 0.260 0.187 0.167 OUTLINE AND MECHANICAL DATA 0.2 4.5 4 4.75 0.167 4.25 0.148 40 (typ.) 0.008 0.177 0.157 Pentawatt V L L1 L8 V V1 V R A B C D1 L5 L2 L3 D R V4 H2 F E V4 V3 E R M1 V V M E1 H3 H1 Dia. L7 L6 RESIN BETWEEN LEADS F1 F H2 G G1 V4 L9 5/6 L4922 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 6/6 |
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